The use of a magnetic tunnel junction element in a memory cell of a non-volatile magnetic random access memory (MRAM) arrays is described in U.S. Pat. No. 5,640,343. A typical MRAM device includes an array of memory cells positioned at the intersections of word lines and bit lines.
A typical memory cell may be composed of a magnetic tunnel junction (MTJ) memory element and a transistor or other non-linear element in series, and intersecting conductive lines. The memory cell is controlled by passing currents through two conductive lines. The MTJ element and the transistor are vertically arranged in the intersection region of the two conductive lines in a vertical space between the two lines to minimize a total MRAM surface area A typical MTJ memory element has a pinned (or fixed) magnetic layer, a free (or sense) magnetic layer, and an insulating tunnel barrier layer sandwiched between the ferromagnetic layers. The MTJ element exhibits a giant tunneling magnetoresistance in the presence of a magnetic field. Relative orientations of magnetization in the free and pinned ferromagnetic layers determine the resistance of the MTJ memory element. Generally, the resistance of the MTJ element is “low” if the magnetic layers have a parallel magnetization orientation, and the resistance is increased considerably if the magnetization orientation is changed from parallel to anti-parallel.
These two combinations of magnetization orientations, parallel and anti-parallel, present logic values of “0” and “1”. The orientation may be changed from parallel to anti-parallel or vice-versa by applying the proper magnetic field to the MTJ memory element. A logic value may be written to an MTJ cell by setting the magnetization orientation in the free layer. The logic value stored in the MTJ cell may be read by sensing the resistance of the MTJ element.
FIGS. 1A and 1B show a schematic view of the structure and function of a MTJ memory cell 20 according to prior art. The memory cell 20 includes a MTJ memory element 12 and transistor 14 connected in series by means of conductive lead 16, conductive stud 14 and contact pad 12, a bit tine 16 and word line 18. The MTJ element 12 is vertically arranged at the intersection region of the bit 16 and word 18 tines. The MTJ memory element 12 is composed of a stack of an insulating tunnel barrier layer 15 sandwiched between two magnetic layers 11 and 13. Orientation of magnetization in both magnetic layers is parallel to a major plane (in-plane orientation) of the layers. One of the magnetic layers has a higher coercivity than that of the other magnetic layer. The magnetic layer 11 with the higher coercivity is normally called “a pinned layer”. The other magnetic layer 13 with the low coercivity is normally called “a free layer”. An antiferromagnetic pinning layer 17 anchors the magnetization orientation in the pinned layer 11 by means of an exchange coupling between the layers.
The orientation of magnetization in the free layer 13 may be changed by a relatively small external magnetic field (a bi-directional arrow). To change the orientation of magnetization in the pinned layer 11 much stronger external magnetic field needs to be applied (an unidirectional arrow). When the magnetization orientations of the free 13 and pinned 11 layers are anti-parallel, the resistance of the MTJ element 12 is high; when the magnetization orientations are parallel the resistance is low. The relative variation of the resistance between these two states may be up to 40% by appropriate choice of MTJ element materials, barrier layer thickness and other parameters.
The MTJ memory element 12 is positioned between the transistor 14 and the current supply bit line 16. In a “write” mode, a current IW1, passing through the line 16 generates a magnetic field 19. The word line 18, orthogonal to the bit line 16 (i.e. in this case the word line 18 is perpendicular to a plane of the FIG. 1A). A current IW2 flowing through the word line 18 generates a second magnetic field 21 (located in the plane of the figure).
In the “write” mode (FIG. 1A), the transistor 14 is blocked. The currents IW1 and IW2 flow through the bit line 16 and the word line 18, respectively. The MTJ element 12 is therefore subjected to two orthogonal magnetic fields 19 and 21, respectively. The field 19 is applied along a hard axis of magnetization in the free layer 13, in order to reduce its switching field. The magnetic field 21 being applied along an easy axis of magnetization in order to generate a reversal of the magnetization of the free layer 13 and thus writes in the memory element 12. In principle, only the memory element 12 located in the intersection region of the lines 16 and 18 is subject to reversal, since each magnetic field 19 or 21 taken individually is insufficient to cause reversal of the magnetization in the free magnetic layer 13.
In a “read” mode (FIG. 1B) the transistor 14 is opened and is held in a saturated condition (i.e. a sense current IS flowing through it is at a maximum) by a positive bias on its gate. The current IS flowing through the bit line 16 only passes through the MTJ memory element 12 whose transistor 14 is opened. This current enables the resistance of the MTJ element 12 to be measured. By comparison with a resistance of a reference memory cell (not shown), a magnetic state of the selected memory cell 20 (“0” or “1”) may thus be determined.
The MTJ memory cells based on in-plane orientation of magnetization in free and pinned magnetic layers suffer from several disadvantages:                (a) MTJ element with in-plane orientation of magnetization in free and pinned magnetic layers require an elongated (rectangular, ellipse and the like) shape of the MTJ element with an aspect ratio (length/width) of 2 or higher in order to insure information storing and to reduce an error probability in the “write” mode. This limits the density of MTJ cells in a MRAM array.        (b) The specified elongated shape of the MTJ elements is difficult to reproduce in sub-micron range of dimensions across a MRAM array composed of thousand elements. The reduction of the MTJ element dimensions results in broadening of a statistical distribution of the element size and shape across the array. Therefore, accidental reverse of the adjacent elements simply by the effect of the magnetic field produced along one of the addressing lines, bit or word, increases.        (c) Number of addressing error in a MRAM array with in-plane orientation of magnetization increases with cell density increase.        (d) The MTJ elements with sub-micron dimensions suffer from instability at elevated temperature of operation.        
All above-mentioned disadvantages limit an application of the MTJ memory cells with in-plane orientation of magnetization in the magnetic layers for high-density MRAM arrays.
A present invention addresses these needs. The invention provides a memory cell for a MRAM array with a perpendicular orientation of magnetization in the pinned and free layers of the MTJ element relative to a major plane of the tunnel barrier layer. The switching field of the MTJ element with the perpendicular magnetization does not require specific shape of the junction and marginally depends on a junction size. Hence, the switching field of the MTJ elements across the MRAM array has a high uniformity. The demagnetizing field in magnetic layers with the perpendicular anisotropy decreases with the reduction of the junction size resulting in an increase of the MTJ element stability. A use of a conductive magnetic flux guide reduces a write current and prevents unwanted magnetization reversal in the MTJ elements along the energized addressing lines.